The FifthGen Parallel Processor is a tree-structured network of processors designed to provide significant performance improvement in the execution of very large time-consuming problems, such as speech recognition and pattern recognition. Earlier versions of tree-structured machines were first designed at Columbia University under DARPA contracts.


FGC’s patented technology includes a novel method and system for interconnecting large numbers of microprocessors in an array formed as a binary tree or similar topology by utilizing an FPGA-based bus controller at each processor node. We believe this method is included in a wide number of computer systems now deployed throughout the world.


 

Binary Tree Architecture


In the binary tree architecture, each Blade Processor Element (BPE) represents a node that branches to two connected nodes, sometimes referred to as the left child and the right child, each of which continues on to the next level. This architecture is especially suited to performcompute–intensive “approximate-match-search” functions that must compare/compute an ‘unknown input’ to a large set of known possibilities, allowing for various forms of distortion and/or incompleteness in the unknown.